1. Field of the Invention
The present invention relates to a test apparatus, a pattern generator, a test method, and a pattern generating method. In particular, the present invention relates to a test apparatus, a pattern generator, a test method, and a pattern generating method for carrying out a delay test of a semiconductor integrated circuit.
2. Description of Related Art
In recent years, development of semiconductor integrated circuit technologies has been remarkable. With such development, there is a demand for carrying out a test of a semiconductor integrated circuit with higher precision.
In a test process for a semiconductor integrated circuit, based on circuit information on a circuit under test (specimen), a test pattern and an expected value pattern, which are configured as a sequence of logical values (digital signal sequence), are prepared in advance. Then, a determination is made as to whether an output pattern output from a specimen based on a clock and an input of the test pattern matches the expected value pattern. When the output pattern matches the expected value pattern, the specimen is determined as a non-defective product, and when the output pattern does not match the expected value pattern, the specimen is determined as a defective product.
Japanese Unexamined Patent Application Publication No. 2004-150820 discloses a test vector generator for generating a test vector for specifying a specific region of a semiconductor integrated circuit, to thereby test the specific region.
As described above, the expected value pattern is obtained based on the circuit information on the circuit under test. In other words, the expected value pattern is determined without accurately considering a process error or the like to be generated during a manufacturing process. Accordingly, the expected value pattern may differ from the output pattern output from the specimen which is to be determined as a non-defective product. Further, there arises a problem in that the specimen to be determined as a non-defective product during the test process is erroneously determined as a defective product during the test process, with the result that the yield of semiconductor integrated circuits deteriorates. Such a problem becomes more serious in a case of testing the circuit under test by a clock having a frequency equal to or greater than a normal operating frequency of the circuit under test.